1. Field of the Invention
The present invention relates to a memory access mechanism, and more particularly, to a method and apparatus for predicting memory access.
2. Description of the Prior Art
FIG. 1 is a diagram of a prior art data processing system 10. As shown in FIG. 1, the data processing system 10 comprises a core processor 101, a memory 102, a cache memory 103, an outer memory interface 104 and an outer memory 105. The core processor 101 is for processing calculation information; the memory 102 is coupled to the core processor 101, and is for storing instructions or data that needs to be processed by the core processor 101; the cache memory 103 is a memory apparatus of low storage capacity but high access speed, and is also coupled to the core processor 101 for temporarily storing instructions or data that needs to be processed by the core processor 101; the outer memory interface 104 is coupled to the core processor 101, for being the communication channel of the outer memory 105 and internal components; and the outer memory 105 is coupled to the outer memory interface 104, and is a memory apparatus of high storage capacity but low access speed.
Generally speaking, the core processor 101 first retrieves instructions and data from the cache memory 103. When the required instructions and data are unable to be found in the cache memory 103, the core processor 101 retrieves the instructions and data from the memory 102. Similarly, when the required instructions and data are unable to be found in the memory 102, the core processor 101 retrieves the instructions and data from the outer memory 105.
Within the procedure of retrieving instructions and data, a memory management unit (MMU) and an address calculation unit (not illustrated in FIG. 1) are set depending on the needs of the system, where the address calculation unit generates a virtual address/logic address according to the tasks of the system, and the MMU is for converting the virtual address/logic address to a physical address, and then searching the overall memory according to the physical address to retrieve the required instructions or data.
The procedure of searching instructions and data from layers of memories is not only time consuming, but also power consuming, and significantly reduces the overall efficiency and performance of the system. Therefore, how to improve the access efficiency of the memory and also reduce the power consumption are important topics to be considered.